Technical Field
The present invention relates to semiconductor processing, and more particularly to processes and devices with improved cut region dielectric fill to avoid shorting between structures.
Description of the Related Art
One commonly employed technique for forming gate structures involves forming a line-type gate electrode structure above a layer of insulating material that is formed above an active region defined in a semiconductor substrate. Typically, the line-type gate electrode structures are formed by defining long parallel line-type structures, i.e., gate electrode structures that extend across multiple spaced-apart active regions and the isolation regions formed in the substrate between such spaced-apart active regions. At some point later in the process flow, these long, line-type gate electrode structures are subsequently “cut” by performing an etching process to define the gate electrodes having the desired length.
After the gate electrodes are patterned, a sidewall spacer is typically formed around the perimeter of the substantially rectangular shaped gate structure, i.e., the spacer is formed adjacent on all four side sidewalls (two sidewalls and two end surfaces) of each of the patterned gate electrodes. In some cases, a thin liner layer may be formed on the gate structure prior to forming the sidewall spacer. The sidewall spacer, in combination with the gate cap layer, functions to protect the gate electrode structure in subsequent processing operations.
In the case where transistor devices are manufactured using so-called gate-first processing techniques, the gate structures (gate electrode plus the gate insulation layer) formed as described above are final gate structures for the device. In the situation where transistor devices are manufactured using so-called gate-last processing techniques, the gate structures (gate electrode and gate insulation layer) formed as described above are sacrificial in nature and will be subsequently removed (after several process operations are performed) and replaced with a final gate structure for the device. In the gate-last processing technique, the final gate structure typically includes one or more layers of high-k insulating material and one or more layers of metal that constitute at least part of the conductive gate electrode of the final gate structure.
Unfortunately, as device dimensions have decreased and packing densities have increased, it is more likely that, when epi semiconductor material is formed in the source/drain regions, some of the epi material may undesirably form on the end surfaces of the polysilicon/amorphous silicon gate electrode. As packing densities have increased, the end-to-end spacing between two different gate electrode structures formed above two different active regions has decreased, thereby limiting the physical size, i.e., the width, of the protective sidewall spacers. Additionally, as the pitch between adjacent gate structures has decreased, the width of the protective sidewall spacers must also be decreased.
For example, in 7 nm technology processing, a few challenges or issues include the following. In replacement metal gate recess processing, the gate length is too narrow, work function metal (WFM) tends to pinch-off during deposition. It is very difficult to recess the WFM if there is a void in the WFM. In forming the gate shape, a spacer image transfer (SIT) process may be employed. A lithography, etch, lithography, etch (LELE) is very difficult to use to pattern the gate shape (however, LELE makes it is easy to define trench shapes). With SIT, it is not straightforward to define certain device types (e.g., WIMPY devices), and separate mask sets are needed for other device types (e.g., for long channel devices). Epi shorts at gate line-ends can occur since pass fins at the line end are so small. Epitaxial lateral growth can easily short source/drains (S/D) around the gate structure. Contact etch shorts at the gate line-end are also issues since there is usually more damage to gate line-ends than line-sides during spacer and contact etches. In addition, the 7 nm spacer target thickness is only 6 nm. While the shorts due to etching may be mitigated with a gate cut last process, this processing would require two flowable oxide fills, which creates a thermal budget issue, especially for high percentage Ge, SiGe fins, and this adds processing time and expense.